Verilog 2 VHDL
VERILOG 2 VHDL CONVERTOR INTRODUCTION We have succeded in making work our first version of a Verilog to VHDL convertor. The convertor was written for a subset of the Verilog grammar, taken from the IEEE specifications. The convertor was implemented on a Linux iv386 machine, using a lexical analyser written in “Lex” (flex), a sintactic analyser written in “Yacc” (bison), a set of ANSI C++ classes and some C sources. The graphic interface was created using Qt v1....