VERILOG 2 VHDL CONVERTOR
INTRODUCTION
We have succeded in making
work our first version of a Verilog to VHDL convertor. The convertor was
written for a subset of the Verilog grammar, taken from the IEEE specifications.
The convertor was implemented on
a Linux iv386 machine, using a lexical analyser written in “Lex” (flex),
a sintactic analyser written in “Yacc” (bison), a set of ANSI C++ classes
and some C sources. The graphic interface was created using Qt v1.45 widgets,
compiled using moc (Meta Object Compiler) and linked with g++ (The GNU
C++ compiler). This interface works on the XFree86 system, version 3.3.4
or above. Sources may be compiled and linked on every UNIX alike machine,
with similar characteristics
HOW CONVERSION WORKS
EXAMPLES
| Verilog source file | VHDL file (after conversion) |
|---|---|
| ADDER.V | ADDER.V2 |
| module adder4 (in1, in2, sum, zero);input [3:0] in1; input [3:0] in2; output [4:0] sum; output zero; reg [4:0] sum,m[0:32]; initial begin sum = 4’b0; zero = 4’b1; end always @(in1 or in2) begin sum = in1 + in2; if (sum == 4’b0) zero = 4’b1; else zero = 4’b0; end endmodule | entity adder4 isport(in1 : in bit_vector(3 downto 0); in2 : in bit_vector(3 downto 0); sum : out bit_vector(4 downto 0); zero : out bit); end adder4; arhitecture VL2VHDL of adder4 is signal m : array (0 to 32) of Bit_vector (4 downto 0); signal sum : Bit_vector (4 downto 0); begin process begin sum <= B”0000″; zero <= B”0001″; end process; block ( in1’event or in2’event ) begin process begin if GUARD then sum <= in1 + in2; if (sum = B”0000″) then zero <= B”0001″; else zero <= B”0000″; endif; end if; wait on GUARD; end process; end block; end VL2VHDL; |
| MARK.V | MARK.V2 |
| module mark1;reg [31:0] m[0:8191]; // 8192 x 32 bit memory reg [12:0] pc; // 13 bit program counter reg [31:0] acc; // 32 bit accumulator reg [15:0] ir; // 16 bit instruction register always begin ir = m[pc]; // fetch an instruction case( ir[15:13]) 3’b000: pc = m[ir[12:0]]; 3’b001: pc = pc + m[ir[12:0]]; 3’b010: acc = -m[ir[12:0]]; 3’b011: m[ir[12:0]] = acc; 3’b100, 3’b101: acc = acc – m[ir[12:0]]; 3’b110: if(acc < 32’b0 ) pc = pc + 13’b1; endcase pc = pc + 13’b1; end endmodule | entity mark1 isend mark1; arhitecture VL2VHDL of mark1 is signal m : array (0 to 8191) of Bit_vector (31 downto 0); signal pc : Bit_vector (12 downto 0); signal acc : Bit_vector (31 downto 0); signal ir : Bit_vector (15 downto 0); begin process begin loop ir <= m(pc); case ir(15 downto 13) is when B”000″ => pc <= m(ir(12 downto 0)); when B”001″ => pc <= pc + m(ir(12 downto 0)); when B”010″ => acc <= -m(ir(12 downto 0)); when B”011″ => m(ir(12 downto 0)) <= acc; when B”101″ | B”100″ => acc <= acc – m(ir(12 downto 0)); when B”110″ => if (acc < B”00000000000000000000000000000000″) then pc <= pc + B”0000000000001″; end if; end case; pc <= pc + B”0000000000001″; end loop; end process; end VL2VHDL; |
ABOUT US
We are three students from the University “Politehnica” of
Bucharest, Computer Science Department. We have done all the work by ourselves.
We would gladly accept any sugestions. Please contact us:
Marilen CORCIOVEI
Razvan MITITEANU
Thank you.
DOWNLOAD
You can download the source code of the program here: v2vhdl-0.6.tgz
DISCLAIMER (updated 27ian2004)
I have made the source of the convertor available under the GPL because of the large number of requests I received. This is a very old work of mine (around 6 years old) which started as a school project. At that time I was just learning yacc and lex and can only imagine the ugly things you will find in there ;). I hope it can help somebody but I am not motivated in developing it further. I only made some small changes to compile with new versions of bison and flex, I do not think the QT part can compile at all.
Comments:
Jose -
As a comment I sugest you to implement the code in Java and put it in a web page. The conversion would be with a simple “past and click” in the web page. Thanks for sharing.
Gunter Königsmann -
Dear len, The link seems to currently require a password. Kind regards, Gunter.